Fractional feedback dividers are utilized in fractional-N PLL synthesis in order to generate clock out signals that are non-integer (i.e., fractional) multiples of the reference clock inputs, thereby increasing the range of synthesized frequencies. Contrary to integer-N PLL synthesis, in which the generated clock out signal can only be integer (i.e., N) multiples of the reference clock inputs, the fractional feedback dividers are able to dynamically modulate the feedback divider ratio between N and N+1 such that the averaged divide ratio, over time, is a fractional number between N and N+1. Therefore, the period of the output clock of the fractional feedback divider will modulate, e.g., in the simplest case, between two different values (i.e., N and N+1). Unfortunately, the modulation in divide ratios also results in jitter (also known as “phase noise” in the frequency domain) at the output clock. Jitter occurs when the output clock is off its ideal position. For example, if the output clock should ideally be at a value between “10” and “11,” jitter will result if the output clock is off that position and is instead at either “10” or “11.” This is due to the fact that the positive edges (i.e., integer values) and negative edges (i.e., fractional values) of the output clock can only line up with the positive edge (i.e., integer values) of the input clock. As such, the output clock will be associated with the wrong frequency when the period of the clock cycle is either “10” or “11.” Specifically, the output clock would be considered too fast when the divide ratio is “10” and too slow when the divide ratio is “11.” Jitter results in error elsewhere as well. For example, in a serial link, jitter increases the likelihood of sampling error during data recovery. Specifically, instead of sampling a signal when intended, it is sampled either too early or too late. The sampled value will therefore not be the intended value, thus resulting in error.
Current solutions address the jitter problem at the output clock of the fractional feedback divider by running the input clock frequency at twice the speed (since jitter is indirectly proportional to the fractional feedback divider input clock frequency). Therefore, by increasing the input clock frequency by a factor of two, the output clock is able to land on twice as many positive edges of the input clock, resulting in a corresponding reduction (i.e., 2×) of the jitter in the output clock. However, increasing the input clock frequency requires a corresponding increase in the power being supplied to the fractional feedback divider (since the input clock frequency is directly proportional to the power being supplied). Further, at the twice the previous input clock frequency, many of the paths (e.g., combinational logic paths) associated with the fractional feedback divider would need to meet timing, which is more difficult at twice the speed.
Accordingly, there is a need for an improved method and apparatus for reducing jitter at the output of the fractional feedback divider without increasing the input clock frequency and with minimal power increase.